1. Field of the Invention
The present invention relates to a system board, and more particularly, to a system board having slots in which a control circuit and modules controlled by the control circuit are mounted.
2. Description of Related Art
A system board for use in a computer system includes slots in which memory modules are mounted and a control circuit to control the memory modules. The slots are regularly arranged at a predetermined distance from the control circuit, and are sequentially connected. Therefore, signal line lengths from the control circuit to the respective slots differ from each other.
Such a signal line arrangement does not cause problems where the computer system operates at a low speed. This is because the computer system can operate normally by connecting the control circuit to the corresponding slots without consideration of signal line lengths from the control circuit to the respective slots.
However, in the case in which the computer system operates at a high speed, such a signal line arrangement could limit operational speed of the computer system.
FIG. 1 is a schematic view illustrating a configuration of a conventional system board for use in a computer system. A main board of the conventional system board includes a memory control circuit 10, slots S1 to S4, signal lines SL, terminal resistors Rt, and a terminal voltage Vt.
First to fourth slots S1 to S4 are successively arranged at a regular interval L. The first slot S1 is arranged at a distance l from the control circuit 10. Signal lines SL are connected to the slots S1 to S4, and the terminal resistors Rt are connected to the corresponding signal lines SL. The terminal voltage Vt is connected to the terminal resistors Rt.
The memory control circuit 10 outputs a command to the slots S1 to S4 via the signal lines SL. The slots S1 to S4 receive or output signals in response to the command from the memory control circuit 10 via the signal lines SL. The terminal resistors Rt and the terminal voltage Vt terminate signals transferred through the signal lines SL.
FIGS. 2A and 2B show upper and lower layers of the system board of FIG. 1.
In general, all of the signal lines SL are not arranged on a single layer. The signal lines SL are divided and arranged on two or more layers. For example, as shown in FIGS. 2A and 2B, the signal lines SL are divided into two groups and arranged on two layers.
Regions S1′ to S4′ denote regions in which the slots S1 to S4 each having 44 pins are mounted, respectively. Signal lines SL1 denote part of the signal lines SL arranged on the upper layer, and signal lines SL2 denote part of the signal lines SL arranged on the lower layer. “h1 to h4” denote via holes arranged in a single row, and “H1 to H4” denote via hole groups each including 11 via holes h1 arranged in a single column. The via holes h1 and h4 are connected to the signal lines, and the via holes h2 and h3 are connected to a ground voltage line and a power voltage line, respectively. The via holes h1 to h4 are filled with a conductive material. Pins of each of the slots S1 to S4 are inserted into the via holes of the via hole groups H1 to H4, respectively, arranged on the regions S1′ to S4′, whereupon the signal lines SL1 and SL2 are connected to the slots S1 to S4, respectively.
As sown in FIG. 2A, the signal lines SL1 are connected to the via holes h4 of the via hole group H4 arranged on the regions S1′ to S4′, respectively. As shown in FIG. 2B, the signal lines SL2 are connected to the via holes h1 of the via hole group H1 arranged on the regions S1′ to S4′, respectively. Even though not shown, the via holes h2 and h3 of the via hole groups H2 and H3 arranged on the regions S1′ to S4′ are connected to the ground voltage line layer and the power voltage line layer.
As shown in FIGS. 2A and 2B, signal line lengths from the memory control circuit 10 to the slots S1 to S4 depend on a location of the slots S1′ to S4′. That is, as a location of the slots S1′ to S4′ becomes distant from the memory control circuit 10, a length of the signal lines SL between the memory control circuit 10 and the slots S1 to S4 increases.
FIG. 3 shows a length of the signal lines according to a location of the slots S1 to S4. As shown in FIG. 3, a distance between the two adjacent slots is “L”. The signal line SL is arranged under the slots S1 to S4 and is branched off at branch points “a” to “d”. Branch signal lines sl 1 to sl 4 are connected to the slots S1 to S4. Lengths of the signal line SL from the memory control circuit 10 to the slots S1 to S4 differ. Accordingly, transmission rates of signals transferred from the memory control circuit 10 to the slots S1 to S4 also differ.
FIG. 4A is a graph illustrating a waveform of a signal transferred from the memory control circuit 10 to the first slot S1. FIG. 4B is a graph illustrating a waveform of a signal transferred from the memory control circuit 10 to the second slot S2. In FIGS. 4A and 4B, the vertical axis denotes a voltage, and the horizontal axis denotes a time period.
Referring to FIG. 4A, a transmission rate transferred from the memory control circuit 10 to the first slot S1 is fast, whereas an amplitude of a signal voltage is narrow, and therefore an eye opening “x” is small.
The eye opening represents signal transmission characteristics. When the eye opening is large, amplitude of the signal voltage becomes large, and therefore the signal transmission characteristic is good. When the eye opening is small, an amplitude of a signal voltage becomes small, and therefore a signal transmission characteristics is bad.
Accordingly, transmission characteristics of the signal transferred from the memory control circuit 10 to the first slot S1 is bad.
Referring to FIG. 4B, a transmission rate of a signal transferred from the memory control circuit 10 to the slot S2 is slow, and an amplitude of the signal voltage is broad, and therefore an eye opening “y” is large. Accordingly, transmission characteristics of the signal transferred from the memory control circuit 10 to the first slot S2 is good.
As described above, the conventional system board has a problem in that signals transferred to the respective slots have a large transmission rate difference with respect to each other. Therefore, even when one slot among several slots has a bad signal transmission characteristic, due to the slot having a bad signal transmission characteristic, performance of the entire system is limited. Also, since the slots have different signal transmission rates, it is difficult to control a signal timing to receive or output a data at an optimum moment.